//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017
//Date        : Sat Feb  3 15:12:15 2018
//Host        : Lenovo-PC running 64-bit major release  (build 9200)
//Command     : generate_target design_1_wrapper.bd
//Design      : design_1_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module design_1_wrapper
   (USER_RGMII_rd,
    USER_RGMII_rx_ctl,
    USER_RGMII_rxc,
    USER_RGMII_td,
    USER_RGMII_tx_ctl,
    USER_RGMII_txc,
    in_axi_aclk,
    in_axi_aresetn);
  input [3:0]USER_RGMII_rd;
  input USER_RGMII_rx_ctl;
  input USER_RGMII_rxc;
  output [3:0]USER_RGMII_td;
  output USER_RGMII_tx_ctl;
  output USER_RGMII_txc;
  input in_axi_aclk;
  input in_axi_aresetn;

  wire [3:0]USER_RGMII_rd;
  wire USER_RGMII_rx_ctl;
  wire USER_RGMII_rxc;
  wire [3:0]USER_RGMII_td;
  wire USER_RGMII_tx_ctl;
  wire USER_RGMII_txc;
  wire in_axi_aclk;
  wire in_axi_aresetn;

  design_1 design_1_i
       (.USER_RGMII_rd(USER_RGMII_rd),
        .USER_RGMII_rx_ctl(USER_RGMII_rx_ctl),
        .USER_RGMII_rxc(USER_RGMII_rxc),
        .USER_RGMII_td(USER_RGMII_td),
        .USER_RGMII_tx_ctl(USER_RGMII_tx_ctl),
        .USER_RGMII_txc(USER_RGMII_txc),
        .in_axi_aclk(in_axi_aclk),
        .in_axi_aresetn(in_axi_aresetn));
endmodule
